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general description the max8563/max8564/max8564a ultra-low-output dual and triple ldo controllers allow flexible and inexpensive point-of-load voltage conversion in motherboards, desknotes, notebooks, and other applications. these parts feature a 0.5v reference voltage with ?% accuracy providing tight regulation of the output volt- age. the max8563 has three n-channel mosfet con- troller outputs, and the max8564/max8564a has two controller outputs. each controller output is adjustable from 0.5v to 3.3v when v dd = 12v and between 0.5v and 1.8v when v dd = 5v. each output is independently enabled and asserts a pok signal when the output reaches 94% of the set value. each output is protected against a soft short-circuit condition by an undervoltage comparator that disables the output when it drops to under 80% of the set voltage for more than 50?. for a catastrophic short condition, the regulators are shut down immediately if the output drops below 60% of the set voltage. the max8563 is available in a 16-pin qsop package, and the max8564/max8564a are available in a 10-pin ?ax package. applications features ? max8563: 3 outputs ? max8564/max8564a: 2 outputs ? 1% feedback regulation ? adjustable output voltage down to 0.5v ? can use ceramic output capacitors ? wide supply voltage range permits operation from 5v or 12v rails ? individual enable control and pok signal allows sequencing ? overload protection against soft short-circuit condition ? undervoltage short-circuit protection ? drive n-channel mosfets max8563/max8564/max8564a 1%, ultra-low output voltage, dual and triple linear n-fet controllers ________________________________________________________________ maxim integrated products 1 ordering information 19-3290; rev 2; 6/06 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin- package pkg code max8563 eee -40? to +85? 16 qsop e16-1 max8564 eub -40? to +85? 10 ?ax u10-2 max8564a eub+ -40? to +85? 10 ?ax u10-2 off on off on off on drv1 fb1 en1 pok1 gnd n.c. drv3 fb3 v dd drv2 fb2 en2 pok2 n.c. pok3 en3 max8563 1.8v 5% in c1 c5 r2 r1 c4 out1 1.5v/1.5a r3 q1 pok1 3.3v 5% in out3 2.5v/2a* c9 c10 c8 q3 r8 r7 r9 r6 r5 r4 c6 c2 c3 c7 q2 out2 1.05v/3a pok2 pok3 5v or 12v in 1.2v 5% in *2.5v output only with v dd = 12v typical operating circuit pin configurations appear at end of data sheet. ?ax is a registered trademark of maxim integrated products, inc. + denotes lead-free package. motherboards dual/triple power supplies desknotes and notebooks graphic cards ultra-low-dropout voltage regulators low-voltage dsp, ?, and microcontroller power supplies
max8563/max8564/max8564a 1%, ultra-low output voltage, dual and triple linear n-fet controllers 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v dd = v en1 = v en2 = v en3 = 5v, v gnd = 0v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ............................................................-0.3v to +14v drv1, drv2, drv3, en1, en2, en3 to gnd............................................-0.3v to (v dd + 0.3v) fb1, fb2, fb3, pok1, pok2, pok3 to gnd ...........-0.3v to +6v continuous power dissipation (t a = +70?) 10-pin ?ax (derate 5.6mw/? above +70?) ........444.4mw 16-pin qsop (derate 8.3mw/? above +70?)........666.7mw operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-65? to +150? lead temperature (soldering, 10s) .................................+300? parameter conditions min typ max units general v dd voltage range 4.5 13.2 v v dd undervoltage-lockout threshold rising, 200mv hysteresis (typ) 3.56 3.76 4.00 v v en_ = v dd = 12v (max8563) 930 1600 v dd quiescent current v en_ = v dd = 12v (max8564/max8564a) 660 1200 ? v dd shutdown current en1 = en2 = en3 = gnd, v dd = 12v 25 ? ldos t a = 0? to +85? 0.494 0.5 0.504 fb_ accuracy t a = -40? to +85? 0.489 0.509 v t a = +25? -100 +100 fb_ input bias current t a = +85? -8 na max8563, max8564 100 drv_ soft-start charging current max8564a 10 ? t a = 0? to +85? 4 drv_ max sourcing current v fb_ = 0.45v t a = -40? to +85? 3 7 ma t a = 0? to +85? 3 drv_ max sinking current v fb_ = 0.6v t a = -40? to +85? 1.8 7 ma v dd = 5v, v fb_ = 0.46v 4.7 drv_ max voltage v dd = 13.2v, v fb_ = 0.46v 8.0 10.9 v fb_ slow short-circuit threshold measured at fb_ (falling) 400 mv fb_ fast short-circuit threshold measured at fb_ (falling) 300 mv slow short-circuit timer 50 ? fb_ to drv_ transconductance 0.115 0.24 0.460 mho logic en_ input low level 0.7 v en_ input high level 1.3 v t a = +25? -0.1 +0.1 en_ input leakage current v en_ = 0 and v dd , v dd = 13.2v t a = +85? 0.001 ?
max8563/max8564/max8564a 1%, ultra-low output voltage, dual and triple linear n-fet controllers _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = v en1 = v en2 = v en3 = 5v, v gnd = 0v, t a = -40? to +85?, unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter conditions min typ max units pok_ threshold falling measured at fb_ (falling) 425 440 455 mv pok_ threshold rising at startup measured at fb_ (rising) 455 470 485 mv pok_ output low level sinking 1ma, v dd = 4.5v, v fb_ = 0.4v 0.1 v t a = +25? 0.1 pok_ output high leakage v dd = 5.5v t a = +85? 0.001 ? note 1: specifications are production tested at t a = +25?. maximum and minimum specifications over temperature are guaranteed by design. typical operating characteristics (circuit of figure 1, t a = +25?.) output voltage vs. input voltage max8563 toc01 input voltage (v) output voltage (v) 1.9 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1.1 1.2 1.3 1.4 1.5 1.6 1.0 1.0 2.0 v dd = 5v v out1 v out2 output voltage vs. input voltage max8563 toc02 input voltage (v) output voltage (v) 3.4 1.4 2.2 2.6 1.8 3.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 1.0 1.0 v dd = 12v v out3 v out1 v out2 output voltage vs. output current max8563 toc03 output current (a) output voltage (v) 2.5 2.0 1.5 1.0 0.5 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0 2.1 2.2 2.3 2.4 2.5 2.6 1.0 03.0 v dd = 12v v out3 v out1 v out2 feedback voltage vs. temperature max8563 toc04 temperature ( c) feedback voltage (v) 60 35 10 -15 0.4988 0.4990 0.4992 0.4994 0.4996 0.4998 0.5000 0.4986 -40 85 v dd = 5v v dd = 12v psrr vs. frequency max8563 toc05 frequency (hz) psrr (db) 10k 1k 10 30 40 20 50 60 70 80 90 100 0 100 100k v out1 = 1.5v v in1 = 2v load = 1.25 v dd = 12v load transient max8563 toc06 i out2 v drv2 v in2 v out2 20mv/div ac-coupled 2v/div 200mv/div ac-coupled 2a/div 0 10 s/div 0 v dd = 12v figure 1, c7 = 100 f 6tpe100mi
max8563/max8564/max8564a 1%, ultra-low output voltage, dual and triple linear n-fet controllers 4 _______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1, t a = +25?.) power-on sequencing with v dd max8563 toc07 v dd v pok1 v in1 v out1 2v/div 2v/div 2v/div 20v/div 20ms/div 0 0 0 0 power-on sequencing with v in max8563 toc08 v dd v pok1 v out1 v in1 2v/div 2v/div 2v/div 20v/div 10ms/div 0 0 0 0 enable configured as shown in figure 4 rd = 100k , re = 4k enable-on sequencing max8563 toc09 v in1 v pok1 v out1 en1 2v/div 2v/div 2v/div 2v/div 20ms/div 0 0 0 0 short-circuit protection max8563 toc10 i out1 v drv1 v out1 5a/div 2v/div 1v/div 20 s/div 0 0 0
max8563/max8564/max8564a 1%, ultra-low output voltage, dual and triple linear n-fet controllers _______________________________________________________________________________________ 5 v dd v dd vl 0.5v pok comparator gm ldo controller 1 ldo controller 2 ldo controller 3 0.5v ref vl uvlo v dd en1 pok1 gnd en2 pok2 en3 pok3 fb3 drv3 drv2 fb1 fb2 drv1 max8563 max8564 max8564a functional diagram pin description name pin max8563 max8564/ max8564a function 1 drv1 drv1 output n-mosfet drive. drives the gate of an external n-channel mosfet to regulate output 1. drv1 is internally pulled to ground when en1 is logic low. connect an external series rc circuit for compensation. see the stability compensation section. 2fb1 fb1 feed b ack inp ut for outp ut 1. c onnect to the center of a r esi stor - d i vi d er b etw een outp ut 1 and gn d to set the outp ut vol tag e of outp ut 1. the feed b ack r eg ul ati on vol tag e i s 0.500v . s ee the outp ut v ol tag e s etti ng secti on. 3 en1 en1 enable control for output 1. drive logic high to enable output 1, or logic low to disable the output. connect to v dd for always-on operation. 4 pok1 pok1 output 1 power-good signal. open-drain output pulls low when output 1 is 12% below the nominal regulated voltage. 5 gnd gnd ground pok2 output 2 power-good signal. open-drain output pulls low when output 2 is 12% below the nominal regulated voltage. 6 n.c. no internal connection
max8563/max8564/max8564a 1%, ultra-low output voltage, dual and triple linear n-fet controllers 6 _______________________________________________________________________________________ pin description (continued) name pin max8563 max8564/ max8564a function en2 enable control for output 2. drive logic high to enable output 2, or logic low to disable the output. connect to v dd for always-on operation. 7 drv3 o utp ut 3 n- m o s fe t d r i ve. d r i ves the g ate of an exter nal n- channel m o s fe t to r eg ul ate outp ut 3. drv3 is internally pulled to ground when en3 is logic low. connect an external series rc circuit for compensation. see the stability compensation section. fb2 feedback input for output 2. connect to the center of a resistor-divider between output 2 and gnd to set the output voltage of output 2. the feedback regulation voltage is 0.500v. see the output voltage setting section. 8 fb3 feedback input for output 3. connect to the center of a resistor-divider between output 3 and gnd to set the output voltage of output 3. the feedback regulation voltage is 0.500v. see the output voltage setting section. drv2 o utp ut 2 n- m o s fe t d r i ve. d r i ves the g ate of the exter nal n- channel m os fe t to r eg ul ate outp ut 2. drv2 is internally pulled to ground when en2 is logic low. connect an external series rc circuit for compensation. see the stability compensation section. 9 en3 enable control for output 3. drive logic high to enable output 3, or logic low to disable the output. connect to v dd for always-on operation. ? dd +5v or +12v supply input. connect to external +5v or +12v supply rail. bypass with a 0.1? ceramic or larger capacitor. 10 pok3 output 3 power-good signal. open-drain output pulls low when output 3 is 12% below the nominal regulated voltage. 11 n.c. no internal connection 12 pok2 output 2 power-good signal. open-drain output pulls low when output 2 is 12% below the nominal regulated voltage. 13 en2 enable control for output 2. drive logic high to enable output 2, or logic low to disable the output. connect to a v dd for always-on operation. 14 fb2 feedback input for output 2. connect to the center of a resistor-divider between output 2 and gnd to set the output voltage of output 2. the feedback regulation voltage is 0.500v. see the output voltage setting section. 15 drv2 o utp ut 2 n- m o s fe t d r i ve. d r i ves the g ate of the exter nal n- channel m os fe t to r eg ul ate outp ut 2. drv2 is internally pulled to ground when en2 is logic low. connect an external series rc circuit for compensation. see the stability compensation section. 16 v dd +5v or +12v supply input. connect to an external +5v or +12v supply rail. bypass with a 0.1? ceramic or larger capacitor.
max8563/max8564/max8564a 1%, ultra-low output voltage, dual and triple linear n-fet controllers _______________________________________________________________________________________ 7 typical application circuits max8563: triple output off on off on off on drv1 fb1 en1 pok1 gnd n.c. drv3 fb3 v dd drv2 fb2 en2 pok2 n.c. pok3 en3 max8563 1.8v 5% in c1 c5 r2 r1 c4 out1 1.5v/1.5a r3 q1 pok1 3.3v 5% in out3 2.5v/2a* c9 c10 c8 q3 r8 r7 r9 r6 r5 r4 c6 c2 c3 c7 q2 out2 1.05v/3a pok2 pok3 5v or 12v in 1.2v 5% in *2.5v output only with v dd = 12v figure 1. max8563 typical application circuit
max8563/max8564/max8564a 1%, ultra-low output voltage, dual and triple linear n-fet controllers 8 _______________________________________________________________________________________ typical application circuits (continued) max8564/max8564a: dual output figure 2. max8564/max8564a typical application circuit max8563 external component list components qty description c1, c3, c8 3 2.2?, 10v x5r ceramic capacitors (optional 100?, 18m , 6.3v aluminum electrolytic, sanyo gtpe100mi in parallel) c2 1 0.1?, 16v x7r ceramic capacitor c4, c7, c9 3 100?, 18m , 6.3v aluminum electrolytic capacitors sanyo gtpe100mi c5, c6, c10 3 1?, 16v x7r ceramic capacitors q1/q2 (dual) 1 dual n-channel mosfets, 30v, 18m fairchild semiconductor fdd6630a r1 1 665 ?% resistor r2 1 620 ?% resistor r3 1 332 ?% resistor r4 1 390 ?% resistor r5 1 182 ?% resistor r6 1 165 ?% resistor r7 1 910 ?% resistor r8 1 1k ?% resistor r9 1 249 ?% resistor max8564/max8564a external component list components qty description c11 1 0.1?, 16v x7r ceramic capacitor c12, c14 2 100?, 18m , 6.3v aluminum electrolytic capacitors sanyo gtpe100mi c15, c17 2 2.2?, 10v x5r ceramic capacitors (optional 100?, 18m , 6.3v aluminum electrolytic, sanyo gtpe100mi in parallel) c18, c20 2 1?, 16v x7r ceramic capacitors q4/q5 (dual) 1 dual n-channel mosfets, 30v, 18m ?% resistor r14 1 182 ?% resistor r15 1 390 ?% resistor r16 1 665 ?% resistor r17 1 332 ?% resistor r18 1 620 ?% resistor off on off on drv1 fb1 en1 pok1 gnd v dd drv2 fb2 en2 pok2 max8564 max8564a 1.8v 5% in c15 c20 r18 r16 c14 out1 1.5v/1.5a r17 q4 pok1 r13 r14 r15 c18 c11 c17 c12 q5 out2 1.05v/3a pok2 5v or 12v in 1.2v 5% in
detailed description the max8563/max8564/max8564a triple and dual ldo controllers allow flexible and inexpensive voltage conversion by controlling the gate of an external n-mosfet in a source-follower configuration. the max8563/max8564/max8564a consist of multiple identical ldo controllers. each ldo controller features an enable input (en_) and a power-ok output (pok_). the max8563/max8564/max8564a also include a 0.5v reference, an internal regulator, and an undervoltage lockout (uvlo). the transconductance amplifier mea- sures the feedback voltage on fb_ and compares it to an internal 0.5v reference connected to the positive input. if the voltage on fb_ is lower than 0.5v, the cur- rent output on the gate-drive output drv_ is increased. if the voltage on fb_ is higher than 0.5v, the current out- put on the gate-drive output is decreased. bias voltage (v dd ), uvlo, and soft-start the max8563/max8564/max8564a bias current for internal circuitry is supplied by v dd . the v dd voltage range is from 4.5v to 13.2v. if v dd drops below 3.76v (typ), the max8563/max8564/max8564a assume that the supply and reference voltages are too low and acti- vate the uvlo circuitry. during uvlo, the internal regu- lator (vl) and the internal bandgap reference are forced off, drv_ is pulled to gnd, and pok_ is pulled low. before any internal startup circuitry is activated, v dd must be above the uvlo threshold. after uvlo indicates that v dd is high enough, the internal vl regulator, the internal bandgap reference, and the bias currents are activated. if en_ is logic-high after the internal reference and bias currents are activated, then the corresponding drv_ out- put initiates operation in soft-start mode. once the voltage on fb_ reaches 94% of the regulation threshold, the full output current of the ldo controller is permitted. when an ldo is activated, the respective drv_ is pulled up from gnd with a typical soft-start current of drv soft- start. the soft-start current limits the slew of the output voltage and limits the initial spike of current that the drain of the external n-mosfet receives. the size of the com- pensation capacitor (c c ) limits the slew rate (see figure 3). this output voltage slew rate is equal to (drv_soft- start /c c )mv/ms, where c c is in ?. the maximum startup drain current is the ratio of c out to c c multiplied by the soft-start current. input voltage (drain voltage of the external n-mosfet) the minimum input voltage to the drain of the n-mosfet is a function of the desired output voltage and the dropout voltage of the n-mosfet. details on calculating this value are covered in the power mosfet selection section. the maximum input voltage to the drain of the n-mosfet is a function of the breakdown voltage and the thermal conditions during operation. the breakdown voltage from drain to source is normally provided in the mosfet data sheet. the theoretical maximum input voltage is the set output voltage plus the breakdown voltage. the thermal constraint is usually the largest concern when discussing maximum input voltage. details on calculating this value are covered in the power mosfet selection section. the mosfet package and thermal relief on the board are the largest contributors to removing heat from the n-mosfet. since output voltage is normally set and maximum output current is fixed, the input voltage becomes the only variable that determines the maxi- mum power dissipated. thus, the maximum input volt- age is limited by the power capability of the n-mosfet, if it is less than the breakdown voltage, which is most often the case. ensure input capacitors handle the maximum input voltage. during a power-up sequence where v dd and en_ rise before the input to the drain of the n-mosfet, the max8563/max8564/max8564a drive drv_ high but the output does not rise. as drv_ rails and v fb_ is still below 80% of the regulation voltage, the max8563/max8564/ max8564a assume that an output short-circuit fault is present and shut down that regulator. to avoid this error condition, connect a resistor-divider from v dd to in_ with the middle node connected to the respective en_ (see figure 4). use the following equations to calculate the resistor values. when v in_ is off or at a low-voltage state: when v in_ is on or at a high-voltage state: 07 . __ > + ? ? ? ? ? ? () + ? r rr vv v e ed dd in in max8563/max8564/max8564a 1%, ultra-low output voltage, dual and triple linear n-fet controllers _______________________________________________________________________________________ 9 drv_ max8563 max8564 max8564a v in_ c c r c c out out1 q1 figure 3. soft-start and compensation schematic
max8563/max8564/max8564a set r d = 100k . the above equations also assume that v dd > v in_ > 1v when v in_ is on or at a high-voltage state, and that v dd > 3v. example: connect 100k from en to v dd and 4k from en_ to in_. thus, when v dd = 12v and v in _ = 0v, then v en _ = 0.46v. when v dd = 12v and v in _ = 1.2v, then v en _ = 1.6v. alternately, to avoid fault shutdown due to the delay of v in relative to v dd , pull en_ low with a separate control logic and only drive high when v in reaches a steady- state value. output voltage the output voltage range at the source of the n-mosfet is from 0.5v to 3.3v when v dd is 12v and from 0.5v to 1.8v when v dd is 5v. the maximum output voltage is a function of the minimum gate-to-source voltage (v gs ) of the mosfet and v dd . the external n-mosfet contains a parasitic diode from source to drain. if the output is ever anticipated to exceed the input, current flows from source to drain. if this is undesirable, external protection is needed. a simple solution is the placement of a diode in series, from in_ to the drain of the n-mosfet, so that reverse current is not possible. due to the forward-voltage drop of the diode, the maximum output voltage is reduced and additional power is consumed in the diode. enable and pok the max8563/max8564/max8564a have independent enable control inputs (en1, en2, and en3). drive en1 high to enable output 1. drive en2 high to enable out- put 2. drive en3 high to enable output 3. when en_ is driven low, the corresponding drv_ is internally pulled to gnd and pok_ is internally pulled low. the pok_ is an open-drain output that provides the sta- tus of the output voltage and pulls low depending upon circuit conditions. during startup, once the fb_ reaches the pok_ threshold, the pok_ signal goes high. the pok_ threshold has 30mv of hysteresis. when the out- put voltage drops 12% below the nominal regulated voltage, pok_ pulls low. all pok_ outputs pull low when uvlo is activated or when the internal vl regula- tor and reference are not ready. output undervoltage and overload protection when an overload event or short circuit occurs, the device that is most vulnerable is the external n-mosfet. the max8563/max8564 /max8564a monitor the output voltage to protect the mosfet. when drv_ is at its maxi- mum voltage and the output voltage drops below 80% but is still greater than 60% of its nominal voltage for more than 50?, the max8563/max8564 /max8564a shut down that particular regulator output by pulling drv_ to gnd. note that there is an additional inherent delay in turning off the mosfet. the delay is a function of the compensation capacitor and the mosfet. if the output recovers to greater than 80% within 50?, it is not considered to be in overload and no action is taken. when the output voltage drops below 60% of its nominal voltage, the max8563/max8564 /max8564a immed iately shut down that particular regulator output by pulling drv_ to gnd. to restart that particular ldo, v dd must be recycled below the uvlo or the corresponding en_ must be recycled. the overload protection is shown in the typical operating characteristics . design procedure output voltage setting the minimum output voltage for each controller of the max8563/max8564/max8564a is typically 0.5v. the maximum output voltage is adjustable up to 3.3v with v dd = 12v, and up to 1.8v with v dd = 5v. to set the out- put voltage, connect the fb_ pin to the center of a volt- age-divider between out_ and gnd (figure 5). the resistor-divider current should be at least 1ma per 1a of maximum output current; i.e., for a 3a maximum output current, set the resistor-divider bias current to 3ma: r v i v ii b fb out min fb out max out max () () () = = 1000 500 i i out min out max () () 1000 13 . __ < + ? ? ? ? ? ? () + ? r rr vv v e ed dd in in 1%, ultra-low output voltage, dual and triple linear n-fet controllers 10 ______________________________________________________________________________________ max8563 max8564 max8564a en_ v dd in_ r d r e figure 4. voltage-divider on en_
to set the output voltage to 0.5v, disconnect r b from fb_ and connect it to out_; this change maintains the minimum load requirement on the output. in this case, r a can vary from 1k to 10k . input and output capacitor selection the input filter capacitor aids in providing low input impedance to the regulator and also reduces peak cur- rents drawn from the power source during transient conditions. use a minimum 2.2? ceramic capacitor from in_ (drain of the external pass n-mosfet) to gnd (see figures 1 and 2). if large line transients or load transients are expected, increase the input capaci- tance to help minimize output voltage changes. the output filter capacitor and its equivalent series resistance (esr) contribute to the stability of the regula- tor (see the stability compensation section) and affect the load-transient response. if large step loads (no load to full load) are expected, and a very fast response (less than a few microseconds) is required, use a 100?, 18m poscap for the output capacitor. if a larger capacitance is desired, keep the capacitance esr product (c out x r esr ) in the 1? to 5? range. if the application expects smaller load steps (less than 50% of full load), then use a 6.8? ceramic capacitor or larger per ampere of maximum output current. this option reduces the size and cost of the regulator circuit. note that some ceramic dielectrics exhibit large capaci- tance variation with temperature. use x7r or x5r dielectrics to ensure sufficient capacitance at all operat- ing temperatures. tantalum and aluminum capacitors are not recommended. power mosfet selection the max8563/max8564/max8564a use an n-channel mosfet as the series pass transistor instead of a p- channel mosfet to reduce cost. the selected mos- fet must have a gate threshold voltage that meets the following criteria: v gs_max v dd - v out_ where v dd is the controller bias voltage, and v gs_max is the maximum gate voltage required to yield the on- resistance (r ds_on ) specified by the manufacturer? data sheet. r ds_on multiplied by the maximum output current (load current) is the maximum voltage dropout across the mosfet, v ds _ min . make sure that v ds _ min meets the condition below to avoid entering dropout, where output voltage starts to decrease and any ripple on the input also passes through to the output: v in_min > v ds _ min + v out where v in_min is the minimum input voltage at the drain of the mosfet. v ds _ min has a positive temperature coefficient; therefore, the value of v ds _ min at the highest operating junction temperature should be used. for thermal management, the maximum power dissipa- tion in the mosfet is calculated by: p d = (v in_max - v out ) x i out_max the mosfet is typically in an smt package. refer to the mosfet data sheet for the pc board area needed to meet the maximum operating junction temperature required. stability compensation connect a resistor, r c , and a capacitor, c c , in series from the drv_ pin to gnd. the values of the compen- sation network depend upon the external mosfet characteristics, the output current range, and the pro- grammed output voltage. the following parameters are needed from the mosfet data sheet: the input capaci- tance (c iss at v ds = 1v), the typical forward transcon- ductance (g fs ), and the current at which g fs was measured (i dfs ). calculate the transconductance of the fet at the maximum load current (i out_max ): gg i i c max fs out max dfs () _ = rr v v rv ab out fb b out = ? ? ? ? ? ? ? ? ? ? ? ? ? ? = () ?? 12 1 max8563/max8564/max8564a 1%, ultra-low output voltage, dual and triple linear n-fet controllers ______________________________________________________________________________________ 11 max8563 max8564 max8564a fb_ out_ r a r b figure 5. adjustable output voltage
max8563/max8564/max8564a for the best transient response in applications with large step loads (see the input and output capacitor selection section for output capacitance requirements), use the following equations to select the compensation components: where c out is the output capacitance and r esr is the esr of c out . to use a low-cost ceramic capacitor (see the input and output capacitor selection section for load-transient response characteristics), use the following equations to select the compensation components: example output 1 of figure 1 is used in this example. table 1 shows the values required to calculate the compensa- tion. the values were taken from the appropriate data sheets and figure 1. pc board layout guidelines due to the high-current paths and tight output accuracy required by most applications, careful pc board layout is required. an evaluation kit (max8563evkit) is available to speed design. it is important to keep all traces as short as possible to maximize the high-current trace dimensions to reduce the effect of undesirable parasitic inductance. the mosfet dissipates a fair amount of heat due to the high currents involved, especially during large input-to-output voltage differences. to dissipate the heat generated by the mosfet, make power traces very wide with a large amount of copper area. an efficient way to achieve good power dissipation on a surface-mount package is to lay out copper areas directly under the mosfet package on multiple layers and connect the areas through vias. use a ground plane to minimize impedance and inductance. in addition to the usual high-power considerations, here are four tips to ensure high output accuracy: ensure that the feedback connection to c out_ is short and direct. place the feedback resistors next to the fb pin. place r c and c c next to the drv_ pin. ensure fb_ and drv_ traces are away from noisy sources to ensure tight accuracy. gsx a a s cx vx fx sx sx m sx v a pf f use f c max c () . . . . . . . . . . ., . == = + ? ? ? ? ? ? + () ? = 30 15 88 12 4 016 1 5 100 12 4 12 4 18 1 12 4 1 5 1 5 2500 0 90 1 2 ? r rx vx fx sx m fsxv a use c . . . . . . , . = + () + () = 59 1 5 100 12 4 18 1 1 124 15 15 599 4 620 ? c cxg gxvi c rx c cxg c out c max c max out out max iss c out c c max () () _ () = + () = ? 15 c vc ggr gvi c r vxcg xr cxg v i c out out c max c max esr c max out out max iss c out out c max esr c c max out out . () () () _ () () _ = + () ? ? ? ? ? ? ? ? + () = + () + ? 016 1 59 1 2 max max () 1%, ultra-low output voltage, dual and triple linear n-fet controllers 12 ______________________________________________________________________________________ table 1. parameters required to calculate compensation parameter conditions value units mosfet c iss v ds = 1v 2500 pf mosfet gfs idfs = 8.8a 30 s v out1 figure 1 1.5 v i out_max figure 1 1.5 a c out1 figure 1 100 ? r esr figure 1 18 m
max8563/max8564/max8564a 1%, ultra-low output voltage, dual and triple linear n-fet controllers ______________________________________________________________________________________ 13 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 drv1 v dd drv2 fb2 en2 pok2 n.c. pok3 en3 top view max8563 qsop fb1 en1 n.c. pok1 gnd drv3 fb3 1 2 3 4 5 10 9 8 7 6 v dd drv2 fb2 en2 pok1 en1 fb1 drv1 max8564 max8564a max pok2 gnd pin configurations chip information transistor count: 1801 process: bicmos
max8563/max8564/max8564a 1%, ultra-low output voltage, dual and triple linear n-fet controllers 14 ______________________________________________________________________________________ package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) qsop.eps f 1 1 21-0055 package outline, qsop .150", .025" lead pitch
max8563/max8564/max8564a 1%, ultra-low output voltage, dual and triple linear n-fet controllers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 15 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. package information (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) 10lumax.eps package outline, 10l umax/usop 1 1 21-0061 rev. document control no. approval proprietary information title: top view front view 1 0.498 ref 0.0196 ref s 6 side view bottom view 0 0 6 0.037 ref 0.0078 max 0.006 0.043 0.118 0.120 0.199 0.0275 0.118 0.0106 0.120 0.0197 bsc inches 1 10 l1 0.0035 0.007 e c b 0.187 0.0157 0.114 h l e2 dim 0.116 0.114 0.116 0.002 d2 e1 a1 d1 min - a 0.940 ref 0.500 bsc 0.090 0.177 4.75 2.89 0.40 0.200 0.270 5.05 0.70 3.00 millimeters 0.05 2.89 2.95 2.95 - min 3.00 3.05 0.15 3.05 max 1.10 10 0.60.1 0.60.1 ? 0.500.1 h 4x s e d2 d1 b a2 a e2 e1 l l1 c gage plane a2 0.030 0.037 0.75 0.95 a1 revision history pages changes at rev 2: 1, 12, 14, 15

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